Many devices including electronic transistors may have three dimensional shapes that are difficult to process using conventional techniques. The topology of such devices may be up-side down, re-entrant, over-hanging, or vertical with respect to a substrate plane of a substrate in which such devices are formed. In order to process such devices such as to grow layers on such topology, improved techniques may be useful that overcome limitations of conventional processing. For example, doping of substrates is often performed by ion implantation in which substrate surfaces that may be effectively exposed to dopant ions are limited by line-of-site trajectories of the ions. Accordingly, vertical surfaces, re-entrant surfaces, or over-hanging surfaces may be inaccessible to such dopant ions. It is with respect to these and other considerations that the present improvements have been needed.